Availability:
     Level 2    , 'j'
     Level E    , 'C'

  Quick Help:
     Read Wedge, j[WedgeAddr],[NumWedges],[NumSkipedWedges],[TranSize],[Opts],[RegAddr0],...,[RegAddr13]
     Read Wedge, C[WedgeAddr],[NumWedges],[NumSkipedWedges],[TranSize],[Opts],[RegAddr0],...,[RegAddr13]

  Description:
    This command reads data from the disk starting at the specified data wedge for the
    specified number of data wedges.  The data is read into the Diagnostic Read Buffer.
    At meanwhile the channel registers are sampled, if the register address are
    specified.

  Input Parameters:

     0 - Wedge Address.
    
         This parameter specifies the address of the first wedge to be read.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to maximum Wedge Address
    
          Default: 0
    
     1 - Transfer Length.
    
         This parameter specifies the number of wedges to be read.
    
          Type:    Unsigned 32-bit value
    
          Range:   0 to 0xFFFFFFFF
    
          Default: If the Wedge Address is entered and the Transfer Length is not
                   entered, then only the specified wedge will be read.
    
                   If both the Wedge Address and Transfer Length are not entered,
                   then the Transfer Length will be set based on the Test Space
                   that is selected.  If the Random Transfer Length option is
                   selected, a random value will be used that is less than or
                   equal to the number of wedges remaining on the track.  If the
                   Random Transfer Length option is not selected, the number of
                   wedges remaining on the track will be read.
    
                   If a Transfer Length is entered, it will be limited to the
                   number of wedges remaining on the track.
    
     2 - Skipped Wedges.
    
         This parameter specifies the number of wedges to skip after each wedge read.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: 0 (Disable wedge skipping)
    
     3 - Wedge Size in NRZ Symbols.
    
         This parameter specifies the number of NRZ symbols to be transfered from
         each wedge.
    
          Type:    Unsigned 32-bit value
    
          Range:   0 to 0xFFFFFFFF
    
          Default: 0 (Use native (max) wedge size)
    
     4 - Options.
    
         This parameter is a bit significant value that selects the following options:
    
             Bit 4 - Bypass the configuration of read channel code rate register
    
                     If this bit is equal to 0, configure channel register to setup read channel
                     in direct write mode. If this bit is equal to 1, bypass the configuration
                     of read channel code rate register.
    
             Bit 3 - Reserved
    
             Bit 2 - Don't swap NRZ symbol data on NRZ bus
    
                     If this bit is equal to 0, NRZ symbol data on NRZ bus will be swapped.
                     If this bit is equal to 1, NRZ symbol data on NRZ bus won't be swapped.
    
             Bit 1 - Continue on Sync Error.
    
                     If this bit is equal to 1, the wedge read operation will not stop when
                     a sync error occurs.
    
             Bit 0 - Formatted Wedge Read.
    
                     If this bit is equal to 1, a formatted wedge read operation will be
                     performed.  If this bit is equal to 0, an unformatted wedge read operation
                     will be performed.  A formatted wedge read attempts to detect a sync mark
                     preceeding the wedge data.  An unfomatted wedge read does not attempt to
                     detect a sync mark before the wedge data.
    
          Type:    Unsigned 32-bit value
    
          Range:   0 to 0xFFFFFFFF
    
          Default: 0x00000001 (Stop on Sync Error, Formatted Wedge Read, Swap NRZ data)
    
     5 - Channel Register Address.
    
         This parameter specifies the address of the 1st Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
     6 - Channel Register Address.
    
         This parameter specifies the address of the 2nd Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
     7 - Channel Register Address.
    
         This parameter specifies the address of the 3rd Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
     8 - Channel Register Address.
    
         This parameter specifies the address of the 4th Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
     9 - Channel Register Address.
    
         This parameter specifies the address of the 5th Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
    10 - Channel Register Address.
    
         This parameter specifies the address of the 6th Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
    11 - Channel Register Address.
    
         This parameter specifies the address of the 7th Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
    12 - Channel Register Address.
    
         This parameter specifies the address of the 8th Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
    13 - Channel Register Address.
    
         This parameter specifies the address of the 9th Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
    14 - Channel Register Address.
    
         This parameter specifies the address of the 10th Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
    15 - Channel Register Address.
    
         This parameter specifies the address of the 11th Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
    16 - Channel Register Address.
    
         This parameter specifies the address of the 12th Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
    17 - Channel Register Address.
    
         This parameter specifies the address of the 13th Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
    18 - Channel Register Address.
    
         This parameter specifies the address of the 14th Read Channel register
         to be read for data collection.
    
          Type:    Unsigned 16-bit value
    
          Range:   0 to 0xFFFF
    
          Default: None
    
  Output Data:

    If no error occurred and one or more read channel register was specified for data
    collection, the following information will be displayed.
    
          "  RegAddr      aaaa      aaaa      aaaa      ... aaaa"
          "  Min          bbbbbbbb  bbbbbbbb  bbbbbbbb  ... bbbbbbbb"
          "  Max          cccccccc  cccccccc  cccccccc  ... cccccccc"
          "  Mean         dddddddd  dddddddd  dddddddd  ... ddddddddd"
          "  StdDev       eeeeee.ee eeeeee.ee eeeeee.ee ... eeeeee.ee"
    
       where
    
          aaaa      is the address of the channel register that was read
    
          bbbbbbbb  is the minimum value that was read from the channel register
    
          cccccccc  is the maximum value that was read from the channel register
    
          dddddddd  is the mean of the values read from the channel register
    
          eeeeee.ee is the standard deviation of the values read from the channel register
    
    If no error occurred, one or more read channel register was specified for data
    collection and Raw ASCII output mode is selected, the following additional
    information will be displayed for each wedge and channel register for which data
    was collected.
    
          "Wedge ffff  RegAddr gggg  RegData hhhhhhhh  Error ii"
    
       where
    
          ffff     is the wedge address
    
          gggg     is the address of the channel register that was read
    
          hhhhhhhh is the value read from the channel register
    
          ii       is the error that was logged for the wedge
    
                      00 = No Error
                      04 = Sync Error
    
    If no error occurred, no read channel registers were specified for data collection
    and the Continue On Sync Error option was selected, the following additional
    information will be displayed.
    
          "Wedges with Sync Errors: jjjj jjjj jjjj ... jjjj"
    
       where
    
          jjjj is the address of a wedge with a sync error
    

    If an error occurred, the following information will be displayed.
    
          "DiagError aaaaaaaa R/W Status c R/W Error dddddddd"
    
       and
    
          "Next User LBA eeeeeeee LLL CHS ffffff.g.hhhh PLP CHS iiiiii.j.kkkk"
          "Remaining Transfer Length llllllll"
    
       or
    
          "Next System LBA eeeeeeee LLL CHS ffffff.g.hhhh PLP CHS iiiiii.j.kkkk"
          "Remaining Transfer Length llllllll"
    
       where
    
          aaaaaaaa is the Diagnostic Error Code
    
          c is the status returned by the R/W subsystem
    
                0 = R/W request completed successfully with error recovery
                1 = R/W request completed successfully (no error recovery performed)
                2 = R/W request failed
    
          dddddddd is the error code returned by the R/W subsystem
    
          eeeeeeee is the Disk Logical Block Address of the sector in error
    
          ffffff is the Logical Cylinder Address of the sector in error
    
          g is the Logical Head Address of the sector in error
    
          hhhh is the Logical Sector Address of the sector in error
    
          iiiiii is the Physical Cylinder Address of the sector in error
    
          j is the Logical Head Address of the sector in error
    
          kkkk is the Physical Sector Address of the sector in error
    
          llllllll is the number of sectors remaining to be read or written
    
    If the Verbose Formatted ASCII Data Output Mode is selected, the Verbose Mode option
    bits will enable the following data to be output when set.
    
       Bit 0:      Enables the R/W Status and R/W Error to be displayed
       Bit 1:      Enable the Next Address to be displayed
       Bit 2:      Enables the Track Position and Track Follow Offset to be displayed
       Bit 3:      Enables the Target Address to be displayed
       Bit 4:      Enables the Recovery Status to be displayed
       Bit 5:      Enables the Fault Status to be displayed
       Bit 6:      Enables the Elapsed Time to be displayed
       Bits 31-7:  NA
    
    If Bit 0 is set, the R/W Status and R/W Error will be displayed even if no error
    occurred.  The data displayed will be formatted as shown above.
    
    If Bit 1 is set, the Next Address will be displayed even if no error occurred.  The
    data displayed will be formatted as shown above.
    
    If Bit 2 is set, the Track Position and Track Follow Offset will be displayed as
    follows.
    
          "Read Position, Persistent Offset m.m% Total Offset n.n%"          or
          "Write Position, Persistent Offset m.m% Total Offset n.n%"         or
          "Write Header Position, Persistent Offset m.m% Total Offset n.n%"
    
       where
    
          m.m is the Persistent Track Follow Offset in units of percentage of track width
    
          n.n is the Total Track Follow Offset in units of percentage of track width
    
    If Bit 3 is set, the Target Address will be displayed as follows.
    
          "Target User LBA pppppppp LLL CHS qqqqqq.r.ssss PLP CHS tttttt.u.vvvv"
          "Starting Transfer Length wwwwwwww"
    
       or
    
          "Target System LBA pppppppp LLL CHS qqqqqq.r.ssss PLP CHS tttttt.u.vvvv"
          "Starting Transfer Length wwwwwwww"
    
       where
    
          pppppppp is the starting Disk Logical Block Address
    
          qqqqqq is the starting Logical Cylinder Address
    
          r is the starting Logical Head Address
    
          ssss is the starting Logical Sector Address
    
          tttttt is the starting Physical Cylinder Address
    
          u is the starting Logical Head Address
    
          vvvv is the starting Physical Sector Address
    
          wwwwwwww is the starting Transfer Length
    
    If Bit 4 is set, the Recovery Status will be displayed as follows.
    
          "Recovered User LBA AAAAAAAA LLL CHS BBBBBB.C.DDDD PLP CHS EEEEEE.F.GGGG"
          "Recovery Flags HHHH Count II"
    
       or
    
          "Recovered System LBA AAAAAAAA LLL CHS BBBBBB.C.DDDD PLP CHS EEEEEE.F.GGGG"
          "Recovery Flags HHHH Count II"
    
       where
    
          AAAAAAAA is the Disk Logical Block Address of the last recovered sector
    
          BBBBBB is the Logical Cylinder Address of the last recovered sector
    
          C is the Logical Head Address of the last recovered sector
    
          DDDD is the Logical Sector Address of the last recovered sector
    
          EEEEEE is the Physical Cylinder Address of the last recovered sector
    
          F is the Logical Head Address of the last recovered sector
    
          GGGG is the Physical Sector Address of the last recovered sector
    
          HHHH are the Recovery Flags reported by the Read/Write code
    
          II is the Recovery Count reported by the Read/Write code
    
    If Bit 5 is set, the Fault Status will be displayed as follows.
    
          "Drive Fault Status JJJJ Preamp Fault Status KKKK"
          "Read Channel Faults:
           SRC Fault Reg 190 = aaaa
           SRC Fault Reg 191 = bbbb
           SID Reg 20B = cccc
           SID Reg 26C = dddd
           SID Reg 26F = eeee
           SID Reg 251 = fffff
    
       where
    
          JJJJ is the Drive Fault Status reported by the Read/Write code
    
          KKKK is the Preamp Fault Status reported by the Read/Write code
    
          aaaa  is the SRC channel fault Register 190h value
    
          bbbb is the SRC channel fault register 191h value
    
          cccc is the SID channel fault register 20bh   value
    
          dddd is the SID channel fault reg 26ch   value
    
          eeee is the SID Channel fault reg 251h value
    
    If Bit 6 is set, the Elapsed Time for the read/write operation will be displayed.

    
       "Elapsed Time a mins b secs"  or
       "Elapsed Time b.c secs"       or
       "Elapsed Time c.d msecs"
    
    where
    
       a is minutes
       b is seconds
       c is milliseconds
       d is microseconds
   
  Examples:
    Example #1:
       To read a single wedge
       (in this case wedge 23 on logical cylinder 45 head 1)

          F3 2>A0
          F3 2>S45,1
          F3 2>j23

    Example #2:
       To read multiple wedges
       (in this case wedges 23 to 26 on logical cylinder 45 head 1)

          F3 2>A0
          F3 2>S45,1
          F3 2>j23,4

    Example #3:
       To read all of the wedges on a track
       (in this case all wedges on logical cylinder 45 head 1)

          F3 2>A0
          F3 2>S45,1
          F3 2>j

    Example #4:
       To read all of the wedges on multiple tracks
       (in this case all wedges on logical cylinders 45 to 49 head 0)

       Note: You must seek to the track before the first one to be read.

          F3 2>A3
          F3 2>S44,0
          F3 2>L,5
          F3 2>j

    Example #5:
       To read all of the wedges on a track and continue on sync errors
       (in this case all logical sectors on logical cylinder 45 head 0)

       Note: An error message will be displayed for each sector in error.

          F3 2>A0
          F3 2>S45,0
          F3 2>j,,,,2

  Revision History:

    0001.0000   Initial revision.
    0001.0001   Increase the number of channel registers for the data collection.
    0002.0000   Added Continue on Sync Error and Formatted Wedge Read options.
    0011.0000   Combined the PSG Diagnostic Error Codes (PSGDEC) and the Diagnostic External
                Test Service Error Codes (DETSEC) into a single set of Diagnostic Error Codes
                (DiagError).